A recent trend in semiconductor memories is to fabricate three-dimensional (3D) semiconductor integrated circuits (ICs). 3D ICs include a variety of structures, such as die on silicon interposer, stacked dies, multi-tiered, stacked complementary metal oxide semiconductor (CMOS) structures, or the like. These 3D circuits offer a host of advantages over traditional two dimensional circuits, such as lower power consumption, higher memory cell density, greater efficiency, alleviating bottlenecks, shorter critical path delays, and lower area cost to name just a few. Stacked die 3D ICs can be constructed by vertically stacking two dimensional chips and providing power and signal communication connections between the chips, such as, for example, using through-substrate vias (TSV). Alternatively, 3D IC can be constructed using a single die with integrated components arranged in three dimensions into a plurality of tiers. Each tier can have its own active device layer and/or interconnect structure. Each pair of adjacent tiers are separated from each other by an insulating layer or thin semiconductor substrate or layer.
The design process for a new IC includes several steps using automated EDA tools. During initial schematic design, the designer identifies a set of functions to include in the design, along with their standard delays. The designer uses computer implemented tools to perform functional simulation, to ensure that the design performs its intended function(s). Before the schematic design is laid out, the designer performs a pre-simulation. The pre-simulation takes into account device and cell characteristics, to provide an estimate of circuit performance (i.e., performance in both analog and digital designs, including timing performance in digital designs). If the design meets circuit performance requirements in the pre-simulation, the designer initiates the floorplan and layout phases, to generate the actual IC layout, using the place and route engine of the EDA tool. If the pre-simulation identifies significant performance issues, the designer modifies the design before proceeding to layout.
Following the layout process, the user verifies the design by using the EDA tools to perform design rule checks (DRC), layout versus schematic (LVS) checks, and resistance-capacitance (RC) extraction.